The manufacturing costs of integrated circuits are largely dependent upon the chip area required to implement desired functions. The chip area, in turn, is defined by the geometries and sizes of the active components such as gate electrodes in metal-oxide-semiconductor (MOS) technology, and diffused regions such as MOS source and drain regions and bipolar emitters and base regions.
With circuit advancement to the very-large-scale integration (VLSI) levels, more and more layers are added to the surface of the wafer. With these additional layers, the geometries and sizes of the active components are determined in part by the photolithography used to establish the horizontal dimensions of the various devices and circuits. The goal is to create a pattern which meets design requirements as well as to correctly align the circuit pattern on the surface of the wafer. Planarization techniques are generally incorporated to offset the effects of a varied topography to achieve the photolithography goals.
In addition to the planarization techniques used to increase photolithographic resolution, the chip area also depends on the isolation technology used. Sufficient electrical isolation must be provided between active circuit elements so that leakage current does not cause functional or specification failures. Increasingly stringent specifications, together with the demand, for example, for smaller memory cells in denser memory arrays, places significant pressure on the isolation technology in memory devices, as well as in other modern integrated circuits.
The size of a memory cell in a memory array also depends upon the particular devices used in the memory cell. The basic SRAM cell, for example, can be formed using cross-coupled CMOS inverters having 2 each n-channel and p-channel transistors. The cell is accessed by, typically, 2 n-channel control gates for a standard SRAM cell and 4 control gates for 2-port memory devices. To conserve physical layout space, the p-channel transistors are often replaced with resistive loads.
Vertical orientation of the various devices used in a memory cell may also achieve additional packing density in VLSI devices. For example, a surrounding gate transistor (SGT) may allow for higher packing densities over the planar transistor counterpart. The SGT, where the gate electrode is arranged vertically around a pillar of silicon, has a source and drain in the pillar and substrate and uses the sidewall of the pillar as the channel. The channel length thus depends upon the height of the pillar and can be changed without changing the occupied area of the transistor. A vertical orientation of the remaining devices within the memory cell in conjunction with the SGT will reduce the area required even further.
It is therefore an object of this invention to provide a method of forming a vertically oriented memory cell which allows for increased packing density by reducing the area required to build the cell while maintaining the electrical integrity and performance of the cell.
It is a further object of this invention to provide such a method which utilizes conventional process flows.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.